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Formal Semantics for VHDL (Hardcover)

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Product Overview

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject. *Author: Kloos, Carlos D./ Delgado Kloos, Carlos/ Breuer, P. *Series Title: Kluwer International Series in Engineering & Computer Science *Series Number: 307 *Binding Type: Hardcover *Number of Pages: 264 *Publication Date: 1995/02/28 *Language: English *Dimensions: 9.21 x 6.14 x 0.63 inches

Specifications

Publisher Springer
Mfg Part# 9780792395522
SKU 213694883
Format Hardcover
ISBN10 0792395522
Release Date 12/28/2009
Product Attributes
Book Format Hardcover
Number of Pages 0264
Publisher Springer
Series Part 307
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